1. Field of the Invention
The present invention relates to a plating method and a plating apparatus, and more particularly to a plating method and a plating apparatus used for filling a fine interconnect pattern formed in a substrate, such as a semiconductor wafer, with metal (interconnect material) such as copper so as to form interconnects.
2. Description of the Related Art
Recently, the so-called damascene process has been used in the art as a process of forming copper interconnects in semiconductor devices. According to the damascene process, fine interconnect recesses such as interconnect trenches in circuit patterns and via holes are formed in an insulating film (inter level dielectric film) laminated on a surface of a semiconductor wafer, and then filled with copper as an interconnect material. Thereafter, extra copper layer (plated film) is removed from the surface by a chemical mechanical polishing (CMP) process or the like to form circuits. It has been studied to use a low-k material having a small dielectric constant as material of the insulating film. For example, low-k/copper damascene interconnects for logic devices is an important technology for producing highly integrated high-performance multi-level interconnects.
The above interconnect forming process poses stringent requirements on copper-plated films. For example, 65 nm generation technology is required to have excellent embeddability with respect to finer damascene structures, excellent in-plane uniformity of a plated film thickness on 300 mm wafers, or reduced steps on a plated film surface. Difficulty will be experienced in satisfying these requirements because barrier and seed layers are expected to be much thinner in the 65 nm generation technology.
If seed layers are formed as thinner layers by conventional cup-type plating apparatus, then the seed layers themselves tend to have higher electric resistance. When a plated film is deposited on a surface of a wafer having such a thinner seed layer, a thickness of the plated film is progressively smaller from an edge of the wafer toward a center thereof. Therefore, in-plane uniformity of the plated film is lost. One solution would be to use an electric field adjustment component known as a shield plate or divided anodes for generating a uniform electric field. However, since components used or a process recipe is changed depending on a type of plating solution and thickness of the seed layer, this solution would require complex operational details if a wide variety of samples are to be fabricated.
According to another countermeasure, electric resistance between an anode and a conductive layer (wafer) may be increased to an extent that in-plane uniformity of a plated film becomes insusceptible to an electric resistance of the seed layer itself. Based on this concept, it has been proposed to lower concentration of sulfuric acid in a plating solution to a level of at most 20 g/L, for example, to increase the electric resistance of the plating solution itself (see U.S. Pat. No. 6,350,366), or to insert a special resistor between electrodes to increase electric resistance between the electrodes (see M. Tsujimura et al., “Novel Compact ECD Tool for ULSI Cu Metallization”, Proc. ISSM, 2000, pp. 106–109).
However, if the concentration of the sulfuric acid in the plating solution is lowered to increase in-plane uniformity of a plated film, then a bottom-up growth of the plated film is reduced as the concentration of the sulfuric acid in the plating solution is lowered, thereby possibly causing a reduction in embeddability in a pattern of fine interconnects. In particular, the above problem manifests itself for interconnects having a width of at most 0.1 μm and via holes having a diameter of at most 0.1 μm, thereby failing to embed a plated film reliably in those interconnects and via holes. Other conventional processes have also suffered such difficulty in depositing plated films having both excellent in-plane uniformity and excellent embeddability.